ASIC Developer at SAP

Compensation

$117,000 – $175,000/yr

Setup: Hybrid
Location: Texas
Type: Full-time
Level: senior
Posted: Sep 11, 2026

Summary from listing

Ericsson is hiring a Senior RTL Design Engineer – Accelerator IP in Austin, Texas, to own the microarchitecture and end-to-end delivery of next-generation L1 accelerator IP. The role translates DSP/FEC and other L1 processing algorithms into high-performance SystemVerilog or Verilog, covers specification, RTL creation, synthesis, timing closure, and verification leadership, and balances power, area, and throughput. The position is hybrid with on-site work in Austin and offers a base salary of $117,000 to $175,000 plus an annual bonus and health benefits.

Required Skills

SystemVerilog/Verilog
DSP/FEC algorithms
ASIC flow
Timing closure
Verification

Additional Information

Required Previous Experiences: Several years of RTL design in complex ASIC/IP environments
End-to-end ASIC flow experience, including coding, linting, CDC, synthesis, and timing closure
Experience translating DSP, FEC, or other L1 processing algorithms into high-performance hardware
Preferred Qualifications: Expert SystemVerilog/Verilog skills
Collaborative teamwork in an intense, creative, close-knit environment