Description
The role focuses on designing and verifying Design for Test (DFT) architectures and test sequences for custom ASICs, including boot-up sequences, scan and BIST logic, coverage checks, DFT constraints, timing closure, CDC, linting, and design debug. It requires a bachelor's degree in electrical engineering or a related field, two years of analog or mixed-signal IC design experience, and experience with SoC integration, design automation, DFT technologies, and ASIC DFT synthesis, STA, simulation, and verification.
