ASIC Digital Design Engineer, HBM PHY RTL at Synopsys

Synopsys is hiring an ASIC Digital Design engineer for its High Bandwidth Memory (HBM) PHY RTL team to develop and deliver RTL for HBM PHY IP. The role focuses on translating architectural requirements into SystemVerilog/Verilog implementations, collaborating with analog, mixed-signal, and physical design teams, solving timing closure and low-power challenges, automating design/verification tasks with scripting, and supporting the ASIC/IP flow through silicon debug and production release. The position requires 7-10 years of ASIC RTL experience and offers a highly collaborative, technically challenging environment.