Description
Synopsys is seeking a senior ASIC digital design and verification engineer to lead the design and verification of complex ASIC blocks and systems. The role involves developing test plans, optimizing performance and power using EDA tools, collaborating with analog, physical design, and applications engineering teams, and mentoring junior engineers. Candidates need a BSEE/MSEE, at least 8 years of ASIC digital design and verification experience, strong RTL expertise, and knowledge of high-performance interface protocols such as PCIe, CXL, DDR, and Ethernet.
