Description
Synopsys is hiring an ASIC Digital Design Engineer to lead scan insertion and ATPG flows for complex ASIC designs, collaborate with RTL and verification teams, resolve DFT issues using Spyglass DFT and scan STA tools, and improve automation and design flows. The role requires 3–10 years of DFT experience, proficiency with EDA tools, digital logic and RTL knowledge, debugging ability, and scripting skills in TCL, Perl, or Python. It is based in Bangalore and offers health, wellness, and financial benefits.
