Description
Synopsys is hiring a Principal RTL Design Engineer, Interconnect IP (PCIe digital design and architecture) in Bengaluru, India. The role owns PCIe digital architecture and RTL design across block, subsystem, and IP-integration levels; defines micro-architecture and implementation strategies; leads design through RTL development, debugging, convergence, and post-silicon support; resolves complex architecture trade-offs; mentors ASIC digital design engineers; and collaborates with verification, physical design, formal, emulation, firmware, and system teams. The position requires a bachelor's degree in Electrical Engineering with 12+ years of ASIC digital design experience, or a master's degree with 10+ years, plus deep PCIe expertise and ASIC design fundamentals. Experience with CXL, DDR, AMBA, UCIe, or related high-speed interconnect protocols is desirable, and familiarity with AI-driven design tools and scripting languages is a plus.
