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ASIC Digital Design, Principal Engineer - 18579 at Synopsys

Location
Hyderabad, Telangana
Type
Full-time
Level
lead/mgmt
Posted

Description

Synopsys is hiring a Principal Digital Verification Engineer focused on memory interface IP, including HBM, DDR, LPDDR, and AMBA. The role involves designing and building SystemVerilog and UVM verification environments, developing test plans and reusable verification IP, driving functional coverage closure, debugging with simulation tools, and mentoring junior engineers. The position is based in Hyderabad, India, and is not eligible for remote work.

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