Description
Synopsys is hiring a Principal ASIC Digital Design Engineer to lead verification strategy, execution, and quality for next-generation PCIe PHY IP products. The role focuses on mixed-signal digital verification, PCIe PHY architectures, LTSSM, link training, power management, equalization, and protocol compliance, using SystemVerilog, UVM, assertions, coverage-driven verification, and debug automation. The engineer will collaborate with design, analog, firmware, architecture, and validation teams, resolve complex failures, mentor engineers, and communicate with internal and customer stakeholders. The position is remote-eligible and based in Mississauga, Canada.
