Description
Synopsys is hiring a senior ASIC digital design engineer to define micro-architecture and develop RTL for mixed-signal and high-speed communication IP, including DDR and HBM interfaces, for high-performance computing and AI infrastructure. The role covers behavioral modeling, synthesis constraints, CDC and RDC analysis, code quality checks, design trade-offs, and mentorship of engineers. Candidates need a master's degree in electrical or computer engineering, at least 10 years of ASIC digital design experience, and deep expertise in DDR, HBM, or similar memory interfaces.
