Description
Synopsys is hiring a Design Verification Sr Engineer in Hanoi to develop and validate verification environments for high-bandwidth interface IP, including digital and mixed-signal designs. The role involves writing SystemVerilog test cases, assertions, and checkers; debugging RTL, gate-level, and co-simulations; driving coverage closure; and collaborating with design, architecture, and silicon validation teams. Candidates need a bachelor's, master's, or PhD in a relevant engineering field, at least two years of design verification experience, and proficiency with SystemVerilog, UVM, VCS, and Verdi. The position is not remote and is part of Synopsys Digital's R&D team in Hanoi.
