Description
Synopsys is hiring a Senior Staff RTL Design Engineer to design and optimize LPDDR PHY IP from microarchitecture through synthesis-ready RTL. The role requires extensive ASIC digital design experience, production RTL ownership, Verilog proficiency, Perl automation, and expertise in synthesis, timing analysis, and power optimization. The engineer will collaborate with architecture, analog, verification, and physical design teams and contribute to design reviews, methodology development, and high-volume mobile, automotive, and AI products. The position is based in Boxborough, Massachusetts, is not remote, and offers a base salary of $138,000–$208,000.
