ASIC Digital Design, Sr Staff Engineer 17919 at Synopsys

Location: Dublin
Type: Full-time
Level: staff+
Posted: Jun 15, 2026

Description

Synopsys is hiring a Senior Staff Engineer for ASIC Digital Design in Dublin, Ireland. The role owns RTL development for automotive digital IP, especially PCIe, DDR, or UCIe controllers, and leads coding, lint, CDC, synthesis, debugging, verification coverage, and ISO 26262 ASIL D safety qualification. The engineer will also mentor teams, apply AI-driven design tools, and support production-quality RTL for automotive SoCs. The position requires a bachelor's degree with 8+ years or a master's degree with 6+ years of relevant experience, along with strong ASIC design, Verilog/System Verilog, and functional-safety expertise.

Required Skills

RTL
PCIe
DDR
UCIe
ISO 26262
Verilog
System Verilog
CDC
Synthesis
DFMEA
FMEDA
DFA

Additional Information

Minimum Education: Bachelor's degree with 8+ years of relevant experience, or a master's degree with 6+ years of relevant experience
Required Previous Experiences: 8+ years of relevant experience with a bachelor's degree, or 6+ years with a master's degree in automotive SoCs or digital IPs
IP-level experience with PCIe, DDR, or UCIe protocols
Experience qualifying embedded hardware systems to ISO 26262 ASIL levels up to ASIL D and using DFMEA, FMEDA, and DFA
Experience writing synthesizable Verilog and System Verilog for ASIC design and simulation tools
Experience with ASIC design flows including lint, CDC, synthesis, static timing analysis, and formal verification
Preferred Qualifications: PCIe experience