ASIC Digital Design, Sr Staff Engineer - 18585 at Synopsys

Synopsys is hiring a Senior Staff Engineer for ASIC Digital Design in Bengaluru, India. The role owns complex subsystem design from requirements and architecture through RTL development, verification collaboration, implementation handoff, and release. Responsibilities include subsystem architecture, Verilog or SystemVerilog RTL, protocol integration, low-power design, synthesis and STA constraints, equivalence checking, and DFT. The position requires a bachelor's or master's degree in a relevant engineering field and at least eight years of hands-on RTL design experience with multiple tape-outs.