Synopsys is hiring an RTL Design Sr Staff Engineer to design and develop high-speed mixed-signal PHY IP blocks in SystemVerilog and Verilog. The role covers micro-architecture specification, RTL design through tape-out, design-quality checks, RTL and gate-level debugging, customer SoC integration and post-silicon support, and mentorship. The position is based in Ho Chi Minh City, Vietnam, and is not eligible for remote work.
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