ASIC Digital Design, Sr Staff Engineer - 18971 at Synopsys

Synopsys is hiring a Sr Staff Mixed-Signal Verification Engineer in Hyderabad to own end-to-end analog-mixed-signal verification for complex IP projects. The role covers AMS test plans, coverage models, UVM and SystemVerilog environments, Verilog-A and Verilog-AMS behavioral modeling, mixed-signal debugging, regression automation, and sign-off, while collaborating with analog designers and other verification teams. The engineer will also mentor verification engineers and drive AMS methodology and best practices. The position requires at least 8 years of hands-on AMS verification experience and is not eligible for remote work.