ASIC Digital Design, Sr Staff Engineer at Synopsys

Synopsys is seeking an RTL Design Engineer to own complex subsystem design from requirements and architecture through RTL development, verification collaboration, implementation handoff, and release. The role involves subsystem architecture, Verilog or SystemVerilog coding, protocol integration, low-power design, synthesis and STA constraints, equivalence checking, and DFT testability. Candidates need a bachelor's or master's degree in a relevant engineering field and at least 8 years of hands-on RTL design experience with multiple tape-outs.