ASIC Digital Design, Sr Staff Engineer at Synopsys

Synopsys is hiring a Senior Staff Engineer for ASIC Digital Design in Yerevan, Armenia. The role focuses on designing RTL modules for UCIe Controller IP, optimizing designs for timing, power, and area across advanced process nodes, developing Python/Tcl/Perl automation, and collaborating with architecture, verification, and physical design teams. The position requires a bachelor's or master's degree in electrical or computer engineering, at least eight years of ASIC digital design experience with RTL ownership in production silicon, and expert Verilog proficiency.