ASIC Digital Design , Sr Staff Engineer at Synopsys

Location: Bengaluru, Karnataka
Level: senior
Posted: Aug 19, 2026

Description

Synopsys is hiring an RTL/IP Design Engineer to design and code high-speed Ethernet IP cores from 100G to 1.6T, translate protocol specifications into micro-architecture and detailed design documents, build directed Verilog testbenches, perform technical reviews, and drive timing closure using synthesis, STA, lint, CDC, and formal verification. The role applies low-power design and automotive safety requirements and collaborates with verification, integration, and product teams across Bangalore, the United States, and other global sites.

Required Skills

RTL design
Verilog
SystemVerilog
Timing analysis
Formal verification
CDC

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering with 8+ years of hands-on ASIC or IP design experience, or a Master's degree with 6+ years
Required Previous Experiences: Deep RTL design experience on IP cores or SoC subsystems that have taped out or shipped to customers
Hands-on experience with Verilog or SystemVerilog, simulation tools, synthesis flows, static timing analysis, lint, CDC, and formal verification tools
Preferred Qualifications: High-speed Ethernet experience at 100G and above