ASIC Digital Design, Staff Engineer-18417 at Synopsys

Location: Hyderabad, Telangana
Type: Full-time
Level: staff+
Posted: Aug 18, 2026

Description

Synopsys is hiring a Staff Engineer for ASIC Digital Design in Hyderabad, India. The role leads verification ownership for critical subsystems, including DDR, HBM, PCIe, UCIe, Ethernet, UALink, and UFS, and is responsible for verification strategy, SystemVerilog and UVM testbenches, complex test cases, coverage closure, regression management, debugging, and mentoring verification engineers. The position requires a bachelor's or master's degree in a relevant engineering field and at least 8 years of ASIC or FPGA verification experience.

Required Skills

SystemVerilog
UVM
Functional coverage
Code coverage
Regression management
Simulation debugging
DDR
PCIe
UCIe

Additional Information

Minimum Education: Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Computer Engineering, or a related technical field
Required Previous Experiences: 8+ years of hands-on ASIC or FPGA verification experience, including ownership of verification deliverables from planning through signoff
Experience developing SystemVerilog and UVM-based testbenches for complex ASIC designs, including assertions, checkers, and constrained random stimulus
Experience technically leading a verification team or mentoring engineers, with demonstrated success collaborating across design, architecture, and verification teams
Experience with verification metrics, regression management, and debugging complex simulation failures in large-scale environments
Preferred Qualifications: Experience with high-speed interface protocols such as DDR, HBM, PCIe, UCIe, Ethernet, UALink, or UFS