ASIC Digital Design, Staff Engineer - 18570 at Synopsys

Synopsys is hiring a Staff ASIC Verification Engineer in Bengaluru to design, implement, debug, and validate System Verilog-based verification environments for DesignWare IP cores. The role covers test planning, functional coverage, regression testing, protocol validation, verification automation, formal verification, and mentoring junior engineers. Candidates need a BSEE with 5+ years or MSEE with 3+ years of relevant ASIC or IP verification experience, along with expertise in UVM/OVM/VMM, simulation tools, scripting, and protocols such as MIPI-I3C, UFS, AMBA, Ethernet, DDR, PCIe, and USB.