ASIC Digital Design, Staff Engineer at Synopsys

Synopsys is hiring an ASIC Verification Engineer to build and maintain UVM-based testbenches, write System Verilog test cases and constrained-random stimulus, develop verification plans, debug RTL and simulation issues, implement assertions and coverage models, and collaborate with design engineers on IP cores for AI, automotive, and cloud applications. The role requires 4–8 years of ASIC or RTL verification experience, familiarity with protocols such as MIPI UFS/UniPro, DDR, PCIe, Ethernet, or USB, and experience with Perforce, scripting, and AI-assisted development tools.