ASIC Digital Design, Staff Engineer at Synopsys

Synopsys is hiring a Front-End (FE) Design Engineer in Porto to design and implement RTL for digital and mixed-signal semiconductor IP. The role covers architecture and specification work, Verilog and SystemVerilog coding, synthesis, timing and power analysis, DFT and ATPG, verification collaboration, documentation, and AI-assisted design workflows. Candidates need a bachelor's or master's degree in a relevant engineering field, at least three years of ASIC digital design or RTL development experience, and strong proficiency in hard description languages, synthesis, timing, and power optimization.