Description
Synopsys is hiring an RTL Design Engineer to architect and implement synthesizable Verilog/SystemVerilog designs for DesignWare IP cores serving commercial, enterprise, and automotive applications. The role covers protocol micro-architecture, data-path and control logic, synthesis, static timing analysis, CDC, linting, P&R-aware synthesis, customer collaboration, technical reviews, debugging, test strategies, and team mentorship. It requires a bachelor's or master's degree in electrical engineering, electronics, VLSI, or a related technical field.
