ASIC Digital Design, Staff Engineer at Synopsys

Synopsys is hiring a Digital Design Engineer focused on Design-for-Testability (DFT) for complex ASIC designs. The role leads scan insertion and ATPG flows, collaborates with RTL and verification teams, resolves DFT issues using Spyglass DFT and scan STA tools, develops automation scripts, and contributes to DFT best practices and silicon validation. The position requires 3–6 years of DFT experience, proficiency with EDA tools, digital logic and RTL knowledge, debugging ability, and scripting skills in TCL, Perl, or Python. It is based in Bangalore and offers health, wellness, and financial benefits.