Description
Experienced ASIC Engineer role on Jane Street’s Ultra Low Latency team, responsible for designing, testing, and deploying advanced hardware designs across FPGA- and ASIC-based technologies. The role emphasizes RTL design and verification, ASIC design using Synopsys or Cadence flows, and collaboration with trading, networking, and research infrastructure teams. The company values improving hardware engineering productivity through tools such as Hardcaml, and is looking for engineers comfortable with programming in high-level languages and open to learning OCaml.
