Description
NVIDIA is hiring an ASIC Engineer to develop and deploy RTL design-quality methodologies for CPU programs, including CDC, RDC, netlist and design auditors, power insertion, lint, and related structural checks. The role analyzes flow results, establishes quality and readiness criteria, collaborates with RTL, DFT, verification, physical-design, and CAD teams, evaluates tool releases, and improves automation, debugging, waiver management, reporting, and training. Candidates need a bachelor’s degree in electrical or computer engineering or equivalent experience, at least three years of ASIC or SoC RTL design or design-methodology experience, Verilog or SystemVerilog build and debugging experience, digital design and microarchitecture knowledge, front-end methodology experience, root-cause analysis skills, and Linux and scripting experience.
