Description
Meta is hiring ASIC Design Engineers for its Infrastructure organization to design cutting-edge ASICs for machine learning, video transcoding, and network acceleration. The role involves architecture exploration, micro-architecture development, identification and integration of soft and hard IP, collaboration with verification, emulation, and implementation teams, and closing designs for timing and power. Candidates must have a bachelor's degree or equivalent practical experience completed before joining, at least two years of experience in micro-architecture and RTL development for complex control and data path IPs or SoC micro-architecture, design, and integration, and RTL development using Verilog, System Verilog, and HLS.
