Description
Meta is hiring an Application-Specific Integrated Circuit (ASIC) Design Verification Engineer to develop and close verification for IP, subsystems, and System on Chip designs supporting data center applications. The role covers verification planning, UVM-based testbench development, functional testing, coverage-driven closure, debugging, and collaboration with design, emulation, model, and silicon validation teams. Candidates need a relevant bachelor's degree or equivalent practical experience, at least two years of SystemVerilog/UVM and/or C/C++ verification experience, and experience with functional verification, EDA tools, scripting, and full verification-cycle infrastructure.
