Description
Meta's Infrastructure Silicon team is hiring a Staff ASIC Design Verification Engineer to lead verification strategy and execution for custom silicon used in data center infrastructure. The role focuses on end-to-end verification of complex IP blocks and SoCs for AI/ML acceleration, networking, and video processing; architecting scalable UVM-based verification environments; defining coverage models; debugging functional failures; and collaborating with design, emulation, and post-silicon validation teams. The position requires a relevant bachelor's degree and at least 8 years of hands-on ASIC verification experience, including SystemVerilog/UVM, IP/SoC verification, functional testing, EDA tools, and verification infrastructure development.
