Description
Meta is hiring an ASIC Design Verification Engineer to develop and close verification for block, IP, subsystem, and SoC designs supporting data center applications. The role covers test planning, SystemVerilog/UVM test-bench development, functional testing, coverage-driven closure, debugging, and collaboration with design, emulation, silicon validation, and other cross-functional teams. Candidates need a completed bachelor's degree in a relevant technical field, at least two years of SystemVerilog/UVM or C/C++ verification experience, and experience with EDA tools and verification scripting.
