Description
Meta is hiring an ASIC Implementation Engineer for its Infrastructure Silicon team to implement complex custom ASICs from RTL through tape-out. The role covers logic and physical synthesis, timing, area, power, congestion, formal verification, RTL linting, DFT, timing constraints, inter-block timing, automation, and handoff support across design, architecture, verification, physical design, emulation, and vendor teams. Candidates need at least two years of front-end synthesis and integration experience, RTL synthesis and design-optimization experience, ASIC tool knowledge, RTL design experience, and experience managing design releases and cross-functional collaboration.
