ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years at 555 Cisco Systems International B.V.

Cisco SiliconOne is hiring an ASIC Engineering Technical Leader to lead design verification for high-performance, high-volume ASICs. The role owns verification activities across RTL, emulation, pre-silicon, and post-silicon phases; develops and improves UVM/System Verilog testbenches, test plans, coverage, emulation infrastructure, and debugging workflows; coordinates with architecture, design, software, and other cross-functional teams; and leads and mentors junior engineers. The position requires a BS/MS and 12+/10+ years of hands-on ASIC design verification experience, along with expertise in System Verilog, UVM, C/C++, hardware emulation, and silicon validation.