ASIC Formal Verification Engineer at Google

Seniority in posting: Mid

Compensation

$163,000 – $237,000/yr

Location: Sunnyvale, California
Type: Full-time
Level: senior
Posted: Jun 2, 2026

Description

Google is hiring an ASIC Formal Verification Engineer to define and execute formal verification for complex IP and SoC designs, including TPU architecture and data-center accelerators. The role covers formal testbenches, SystemVerilog Assertions, verification flows, sign-off metrics, and guidance of design and verification teams. Candidates need a bachelor's degree in a relevant engineering or computer science field and at least eight years of silicon development or ASIC/SoC design experience, with formal verification expertise. The position offers $163,000–$237,000 USD plus a 15% bonus target, equity, and benefits.

Required Skills

Formal verification
SystemVerilog Assertions
Formal testbenches
Continuous integration
Data-path verification
Equivalence checking
Connectivity checking

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
Required Previous Experiences: 8 years of experience in silicon development or ASIC/SoC design
Experience with SystemVerilog Assertions and formal verification methods
Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture
10 years of experience with industry-standard tools, languages, and methodologies for silicon-based IC and chip development
Experience with formal verification platforms such as Cadence Jasper, Synopsys VC Formal, or Siemens Questa Formal
Experience with data-path verification, sequential equivalence checking, and connectivity checking
Experience formally proving the correctness of floating-point adders and multipliers
Experience with schedulers, NoCs, networking topologies, and AXI/AMBA protocols