Description
The Full Chip Static Timing Analysis (STA) Engineer owns final timing closure for ASIC designs, including PVT-corner sign-off, SDC constraint development, multi-mode multi-corner analysis, timing ECOs, and automation using Tcl, Python, and Perl. The role requires a bachelor’s degree in electrical or computer engineering, at least 12 years of ASIC STA and timing-closure experience, and expertise with Cadence or Synopsys tools. The annual base salary is USD 143,800 to USD 230,000, with discretionary bonus, equity, and medical, dental, and vision benefits.
