Description
Meta is hiring ASIC Frontend Implementation Engineers for its Infrastructure organization. The role focuses on front-end ASIC implementation from RTL through netlist, including clock-domain and reset-domain crossing analysis, RTL linting, DFT coverage, synthesis optimization, automation, and handoff support across design, verification, emulation, and physical design teams. Candidates need a relevant bachelor's degree or equivalent practical experience, at least six years of static verification tool experience, and experience with ASIC front-end flows, SystemVerilog or another HDL, and cross-team communication.
