ASIC Logic Design Verification Principal Engineer at Synopsys

Location: Dublin
Type: Full-time
Level: staff+
Posted: Sep 2, 2026

Description

Synopsys is hiring a Principal Engineer for ASIC Logic Design Verification in Dublin, Ireland. The role focuses on interface IP verification, including UVM testbench architecture, System Verilog sequences and assertions, constrained random stimulus, coverage analysis, formal verification, and mentoring verification engineers. Candidates need a bachelor’s or master’s degree in a relevant engineering field and at least 12 years of ASIC design verification experience, with strong UVM, System Verilog, and programming skills.

Required Skills

UVM verification
System Verilog
Constrained random
Coverage-driven
System Verilog Assertions
Formal verification
PCI Express
CXL protocols

Additional Information

Minimum Education: Bachelor’s or master’s degree in computer engineering, Electrical Engineering, or Communication Engineering
Required Previous Experiences: 12+ years of hands-on ASIC design verification experience focused on UVM-based functional verification
Experience implementing System Verilog Assertions for functional and formal verification flows
Experience with interface IP verification, formal verification tools, and AI-assisted coding tools
Preferred Qualifications: Experience with PCI Express and CXL protocols
Experience with interface IP verification, Jasper or VC Formal, and Cursor or GitHub Copilot