Description
The role develops custom silicon solutions for Google's direct-to-consumer products by implementing ASIC RTL-to-GDS designs and managing block and full-chip physical implementation and quality-of-results metrics, including power, timing, and area. It requires a bachelor's degree in Electrical Engineering or Computer Science or equivalent practical experience, 8 years of physical design engineering experience, and experience managing high-performance CPU or GPU design schemas; a master's degree and power-optimization experience are preferred.
