ASIC Physical Design Engineer at ralliant

Tektronix is hiring an experienced ASIC Physical Design Engineer to work on SOC physical design and implementation from RTL or gate-level netlist through GDSII. The role covers floorplanning, power planning, place-and-route, clock tree synthesis, routing, timing analysis and closure, physical signoff, and collaboration with RTL, verification, DFT, analog, packaging, and product architecture teams. The position is based in Louisville, Colorado or Beaverton, Oregon, requires a BS in Electrical Engineering or equivalent experience and 5+ years of ASIC physical design experience, and offers a salary range of 148,900.00–276,500.00 in local currency.