Description
NVIDIA is seeking an ASIC-PD engineer to work from RTL freeze through tapeout, including synthesis, formal verification, constraint creation, timing closure and sign-off, chip partitioning and floorplanning, special-mode timing closure, ECO creation, and automation of the timing closure flow. The role requires an MS in EE or Microelectronics, IC design implementation experience, and coursework in circuit and digital design; Synopsys and Cadence EDA experience, Python or TCL proficiency, and English reading and writing skills are helpful.
