ASIC Physical Design, Sr Staff Engineer - 16724 at Synopsys

Synopsys is hiring a Senior Staff ASIC Physical Design Engineer to lead physical design implementation for complex test chips and PHY IP across DDR, HBM, and UCIe protocols. The role owns RTL-to-GDSII flow, floorplanning, power and ground strategies, timing closure, static timing analysis, physical verification, IP and macro integration, tool automation, and tape-out documentation. Candidates need at least 9 years of ASIC physical design experience, expertise in advanced process nodes and industry-standard EDA tools, and authorization to work in the United States. The position is remote-eligible and is part of Synopsys’s Test Chip PHY development team.