ASIC Physical Design, Staff Engineer - 18116 at Synopsys

Synopsys is hiring a Mixed-Signal Physical Design Engineer to lead the physical implementation of high-speed interface IPs and test chips from RTL through GDSII, including timing and physical sign-off. The role involves cross-functional IP integration and verification, technical guidance and mentorship, process improvement, and delivery of reliable physical design solutions. Candidates need a BE or MSEE, at least four years of direct physical design experience, full-cycle IC design knowledge, and advanced PnR and sign-off skills.