ASIC Physical Design, Staff Engineer in District 7 at Synopsys

Synopsys is hiring a Digital Physical Design Engineer to drive RTL-to-GDS implementation for high-speed interface IP such as SerDes, DDR, HDMI, MIPI, and USB at 7nm, 5nm, and 3nm nodes. The role covers synthesis, floorplanning, power planning, clock tree synthesis, placement, routing, physical verification, timing closure, EMIR signoff, IR-drop and electromigration analysis, and automation using Synopsys EDA tools and scripting languages. The engineer will collaborate with RTL, verification, product, and customer teams and provide technical support during IP integration.