ASIC Power Manager, ML Accelerators at Google

Seniority in posting: Advanced

Compensation

$192,000 – $278,000/yr

Location: Sunnyvale, California
Type: Full-time
Level: lead/mgmt
Posted: Sep 24, 2026

Description

Google is hiring a Power Design Manager to lead a team responsible for ASIC and SoC power architecture, power optimization, power modeling, and system power integration for TPU designs. The role owns complex technical projects from concept through closure, defines power-efficiency processes and tools, and collaborates with software, system, IP, and chip vendors. Candidates need a bachelor's degree in a relevant engineering or computer science field and 10 years of ASIC or SoC design experience, with additional experience in power design, power management architectures, and pre- and post-silicon power measurement preferred.

Required Skills

Power architecture
Power optimization
Power modeling
RTL design
Power management
DVFS

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience
Required Previous Experiences: 10 years of ASIC or SoC design experience
Experience with power design, power modeling, power architecture, or power reduction methodologies/techniques
Preferred Qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, or Computer Science with an emphasis on computer architecture
5 years of experience managing mid-sized ASIC/SOC design teams focused on power design and optimization
Experience defining and implementing chip-wide power management architectures and designs
Experience in power modeling, measurement, and correlation across pre- and post-silicon phases
Understanding of modern power and thermal management techniques at silicon and system levels, including DVFS, Turboing, thermal management, and system-level tradeoffs
Ability to solve open-ended power and performance problems under ambiguity
Translation Company Name: Google