Description
Hewlett Packard Enterprise is hiring an ASIC Principal Engineer to define and architect high-performance networking ASIC blocks, perform micro-architecture and logic design, collaborate on verification and physical design, and debug timing and test failures. The role requires strong Verilog RTL coding, knowledge of high-performance memory and clock synchronization, and 15 or more years of experience with an MSEE or BSEE. It is a hybrid position requiring an average of two days per week at an HPE office.
