ASIC RTL Design Engineer at Google

Compensation

$116,000 – $165,000/yr

Location: Sunnyvale, California
Type: Full-time
Level: mid
Posted: Sep 10, 2026

Description

Google is hiring an ASIC RTL Design Engineer to define and implement TPU microarchitecture and SoC-level register-transfer-level designs, primarily in SystemVerilog. The role covers top-level RTL, architecture, global communication buses, complex ASIC integration, verification collaboration, physical-design requirements, and design-flow development. Candidates need a relevant bachelor's degree or equivalent practical experience and at least two years of ASIC RTL design experience.

Required Skills

SystemVerilog
SoC RTL design
Microarchitecture
Bus protocols
Digital logic
State machines
Power analysis

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related technical field, or equivalent practical experience
Required Previous Experiences: 2 years of ASIC RTL design experience using SystemVerilog or Verilog
Experience with industry-standard EDA tools for simulation, synthesis, and power analysis
Experience with digital design, synchronous and asynchronous logic, state machines, and bus protocols