ASIC/RTL Design Engineer for High-speed Interfaces at Qualcomm International Inc., Mexico Branch Office

Qualcomm Technologies, Inc. is hiring a Mixed-Signal IP Micro-Architecture and Digital Design Engineer to architect, implement, and validate high-performance, low-power interface IPs such as SerDes, DDR, and die-to-die interconnects. The role covers micro-architecture and RTL development, ASIC design tools, DFT, verification, physical design support, and SoC integration. Candidates need a master’s degree in electrical or computer engineering and 7+ years of RTL and ASIC design experience, with 5+ years in mixed-signal IP micro-architecture and digital design. The disclosed pay range is $145,600 to $218,400.