ASIC/SoC Design Engineer at Google

Seniority in posting: Advanced

Language

Location: Tel Aviv, Tel-Aviv District · Haifa, Haifa District
Level: not_specified
Posted: Sep 15, 2026

Description

The ASIC/SoC Design Engineer will contribute across the full ASIC design lifecycle, from specification through production, by defining block-level designs, developing RTL in Verilog, SystemVerilog, or VHDL, debugging and verifying designs, supporting synthesis and timing/power closure, and participating in FPGA and silicon bring-up. The role collaborates with architecture, software, verification, power, timing, synthesis, and other teams, and requires a bachelor's degree in Electrical Engineering or equivalent practical experience plus ASIC design, verification, synthesis, timing/power analysis, DFT, and SoC development experience.

Required Skills

RTL development
Verilog
SystemVerilog
VHDL
Synthesis
Timing/Power analysis
Design for Testing
FPGA
Python

Additional Information

Minimum Education: Bachelor's degree in Electrical Engineering or equivalent practical experience
Required Previous Experiences: ASIC design verification, synthesis, timing/power analysis, and Design for Testing (DFT) experience
ASIC development experience with Verilog, SystemVerilog, VHDL, or Chisel
System on a Chip (SoC) development cycle experience
Preferred Qualifications: Proficiency with a scripting language such as Python or Perl
Knowledge of high-performance and low-power design techniques
Knowledge of assertion-based formal verification
Knowledge of FPGA and emulation platforms
Knowledge of SoC architecture
Knowledge of arithmetic units, bus architectures, processor design, accelerators, or memory hierarchies