Description
The role leads a complex ASIC subsystem and contributes to the full System-on-Chip design cycle, including architecture, RTL development, micro-architecture, block partitioning, interfaces, verification, synthesis, and timing closure. The position requires a bachelor's degree in Electrical Engineering or equivalent practical experience, five years of RTL development experience, and expertise with speed interfaces, micro-architecture, verification, synthesis, and timing closure. Preferred qualifications include scripting, processor and memory design, low-power techniques, FPGA and emulation platforms, and formal verification. The position is based in Haifa or Tel Aviv, Israel, and typically requires in-person interviews.
