ASIC/SoC RTL Design Engineer at Google

Google is hiring an ASIC/SoC RTL Design Engineer to develop management and control subsystems for TPU and data-center accelerator chips. The role involves creating microarchitecture specifications, writing SystemVerilog RTL, collaborating with architecture, power, design validation, and physical design teams, and supporting chip management, clocking, reset, debugging, and SoC infrastructure. Candidates need a bachelor's degree in a relevant engineering or computer science field and at least eight years of ASIC design experience, along with SystemVerilog, scripting, and digital design expertise.