Description
The role leads a complex ASIC subsystem for Google's Edge-AI and direct-to-consumer products, defining high-performance hardware/software interfaces, micro-architecture, block partitioning, and design flows. The position collaborates with software, verification, and physical design teams to ensure correct and performant designs, and requires a bachelor's degree in Electrical Engineering or equivalent practical experience, three years of RTL development using Verilog, and experience with speed interfaces and ASIC design activities.
